1. Field of the Invention
The present invention relates generally to copper interconnects. More particularly, the present invention relates to a partial-via-first copper dual damascene process utilizing a TEOS-based oxide cap layer having reduced carbon content, which is capable solving via self-etching stop problem.
2. Description of the Prior Art
Damascene interconnect processes incorporated with copper are known in the art, which are also referred to as “copper damascene processes” in the semiconductor industry. The copper damascene processes provide a solution to form a conductive wire coupled with an integral via plug without the need of dry etching copper. Either a single damascene or a dual damascene structure is used to connect devices and/or wires of an integrated circuit. Generally, the dual damascene process encompasses trench-first, via-first, partial-via-first, and self-aligned processes.
FIGS. 1-5 are schematic, cross-sectional diagrams showing a conventional partial-via-first dual damascene process. As shown in FIG. 1, a substrate 1 having thereon a base layer or a lower low-k dielectric layer 10 is provided. A lower copper wiring 12 is inlaid into the lower low-k dielectric layer 10. The lower copper wiring 12 and the low-k dielectric layer 10 are covered with a lower cap layer 14. A low-k dielectric layer 16, a silicon oxide cap layer 18, a metal hard mask layer 20 and a bottom anti-reflective coating (BARC) layer 22 are sequentially deposited on the lower cap layer 14. A layer of photoresist (Trench Photo) 30 having a trench opening 32 therein is formed on the BARC layer 22.
Subsequently, as shown in FIG. 2, a dry etching process is carried out. A trench recess 36 is etched into the metal hard mask layer 20 and the silicon oxide cap layer 18 through the trench opening 32. The dry etching stops on the silicon oxide cap layer 18. The remaining photoresist 30 and BARC layer 22 are then stripped off.
As shown in FIG. 3, another BARC layer 38 is coated over the substrate 1 and fills the trench recess 36. A layer of photoresist (Via Photo) 40 is then formed on the BARC layer 38. The photoresist layer 40 has a via opening 42 patterned by using conventional lithographic methods. The via opening 42 is situated directly above the trench recess 36.
As shown in FIG. 4, using the photoresist layer 40 as an etching hard mask, the BARC layer 38, the silicon oxide cap layer 18, and the lower low-k dielectric layer 16 are etched through the via opening 42, thereby forming a partial via feature 46 in an upper portion of the dielectric layer 16. The remaining photoresist layer 40 and the BARC layer 38 are stripped off by using oxygen plasma.
As shown in FIG. 5, using the metal hard mask layer 20 as an etching hard mask, a dry etching is performed to etch away the silicon oxide cap layer 18 and the lower low-k dielectric layer 16 through the trench recess 36 and the partial via 46, thereby forming a dual damascene opening 50 comprising a trench opening 56 and a via opening 66.
The via opening 66 is supposed to expose a portion of the underlying inlaid copper wiring 12. However, as indicated in FIG. 5, as the critical dimension of the via hole shrinks to 90 nanometers or beyond, the via etching stops before the lower copper wiring 12, and thus fails to open the lower copper wiring 12. This via self-etching stop problem becomes worse when the via opening is an isolated via.
In light of the above, there is a need in this industry to provide an improved method of forming dual damascene structure in the fabrication of integrated circuits, which is capable of solving the aforesaid via self-etching stop problem.